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| White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY* 512MB - 64Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture PC2700 @ CL 2.5 Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh, (8K/64ms refresh) Serial presence detect with EEPROM Power supply: * VCC = VCCQ = +2.5V 0.2V 184 pin DIMM package * D3 PCB height: 28.58mm (1.125") NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option * This product is under development, is not qualified or characterized and is subject to change without notice. DESCRIPTION The WV3EG64M72ETSU is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of nine 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. OPERATING FREQUENCIES DDR333 @CL=2.5 Clock Speed CL-tRCD-tRP 166MHz 2.5-3-3 October 2005 Rev. 0 1 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY PIN CONFIGURATION PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC NC VSS DQ8 DQ9 DQS1 VCCQ CK1 CK1# VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS A1 CB0 CB1 VCC PIN 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 SYMBOL DQS8 A0 CB2 VSS CB3 BA1 DQ32 VCCQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VCCQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 VCC NC DQ48 DQ49 VSS CK2# CK2 VCCQ DQS6 DQ50 DQ51 VSS VCCID DQ56 DQ57 VCC DQS7 DQ58 DQ59 VSS NC SDA SCL PIN 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 SYMBOL VSS DQ4 DQ5 VCCQ DM0 DQ6 DQ7 VSS NC NC NC VCCQ DQ12 DQ13 DM1 VCC DQ14 DQ15 NC VCCQ NC DQ20 A12 VSS DQ21 A11 DM2 VCC DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VCCQ DM3 A3 DQ30 VSS DQ31 CB4 CB5 VCCQ CK0 CK0# PIN 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 SYMBOL VSS DM8 A10 CB6 VCCQ CB7 VSS DQ36 DQ37 VCC DM4 DQ38 DQ39 VSS DQ44 RAS# DQ45 VCCQ CS0# NC DM5 VSS DQ46 DQ47 NC VCCQ DQ52 DQ53 NC VCC DM6 DQ54 DQ55 VCCQ NC DQ60 DQ61 VSS DM7 DQ62 DQ63 VCCQ SA0 SA1 SA2 VCCSPD A0-A12 BA0-BA1 DQ0-DQ63 DQS0-DQS8 CB0-CB7 CK0, CK1, CK2 CK0#, CK1#, CK2# CKE0 CS0# RAS# CAS# WE# DM0-DM8 VCC VCCQ VSS VREF VCCSPD SDA SCL SA0-SA2 VCCID NC PIN NAMES Address input (Multiplexed) Bank Select Address Data Input/Output Data Strobe Input/Output Check Bits Clock Input Clock Input Clock Enable input Chip Select Input Row Address Strobe Column Address Strobe Write Enable Data-in-mask Power Supply Power Supply for DQS Ground Power Supply for Reference Serial EEPROM Power Supply Serial data I/O Serial clock Address in EEPROM VCC Indentification Flag No Connect Octobert 2005 Rev. 0 2 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY FUNCTIONAL BLOCK DIAGRAM CS0# DQS0 DM0 DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS8 DM8 CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS *Clock Net Wiring DRAM 1 1.5PF DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM DQ7 DQ6 DQ1 DQ0 DQ5 DQ4 DQ3 DQ2 CS# DQS R = 120 Ohm Card Edge DRAM 3 1.5PF DRAM 5 1.5PF DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 CS# DQS Clock Wiring Clock Input CK0, CK0# CK1, CK1# CK2, CK2# SERIAL PD DDR SDRAMs 2 DDR SDRAMs 3 DDR SDRAMs 3 DDR SDRAMs SCL WP SDA A0 A1 A2 SA0 SA1 SA2 BA0-BA1 A0-A12 RAS# CAS# CKE0 WE# BA0-BA1: DDR SDRAMs A0-A12: DDR SDRAMs RAS#: DDR SDRAMs CAS#: DDR SDRAMs CKE: DDR SDRAMs WE#: DDR SDRAMs VCCSPD VCC/VCCQ VREF VSS SPD DDR SDRAMs DDR SDRAMs DDR SDRAMs NOTE: All datalines are terminated through a 22 ohm series resistor. Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS# relationships must be maintained as shown. Octobert 2005 Rev. 0 3 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Voltage on VCCQ supply relative to VSS Storage Temperature Operating Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC VCCQ TSTG TA PD IOS Value -0.5 to 3.6 -1.0 to 3.6 -1.0 to 3.6 -55 to +150 0 to +70 9 50 Units V V V C C W mA Note: Permanent device damage may occur if `ABSOLUTE MAXIMUM RATINGS' are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability 0C TA 70C, VCC = VCCQ = 2.5V 0.2V Parameter Supply voltage DDR266/DDR333 (nominal VCC of 2.5V) I/O Supply voltage DDR266/DDR333 (nominal VCC of 2.5V) I/O Reference voltage I/O Termination voltage Input logic high voltage Input logic low voltage Input voltage level, CK and CK# Input differential voltage, CK and CK# Input crossing point voltage, CK and CK# Addr, CAS#, RAS#, WE# CS#, CKE CK, CK# DM Symbol VCC VCCQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VIX(DC) Min 2.3 2.3 0.49*VCCQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.3 -18 -18 -6 -2 -5 -16.8 16.8 -9 9 Max 2.7 2.7 0.51*VCCQ VREF+0.04 VCCQ+0.30 VREF-0.15 VCCQ+0.30 VCCQ+0.60 VCCQ+0.60 18 18 6 2 5 -- -- -- -- Unit V V V V V V V V uA uA uA uA uA mA mA mA mA Note DC CHARACTERISTICS 1 2 3 Input leakage current II Output leakage current Output high current (normal strengh); VOUT = V +0.84V Output high current (normal strengh); VOUT = VTT -0.84V Output high current (half strengh); VOUT = VTT +0.45V Output high current (half strengh); VOUT = VTT -0.45V IOZ IOH IOL IOH IOL NOTES: 1. VREF is expected to be equal to 0.5*VCCQ of the transmitting device, and to track variations in the DC level of the same. Peak to peak noise on VREF may not exceed 2% of the DC value 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3. VID is the magnitude of the difference between the input level on CK and the input level on CK#. CAPACITANCE TA = 25C, f = 1MHz, VCC = VCCQ = 2.5V Parameter Input Capacitance (A0-A12, BA0-BA1, RAS#, CAS#, WE#) Input Capacitance (CKE0) Input Capacitance (CS0#) Input Capacitance (CK0 to CK2, CK0# to CK2#) Input Capacitance (DM0-DM7) Data and DQS input/output capacitance (DQ0-DQ63) Octobert 2005 Rev. 0 4 Symbol CIN1 CIN2 CIN3 CIN4 CIN5 COUT1 Min 22 22 22 10 8 8 Max 31 31 31 13 9 9 Unit pF pF pF pF pF pF White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs 0C TA 70C, VCC = VCCQ = 2.5V 0.2V Includes DDR SDRAM component only WV3EG64M72ETSU-D3 PRELIMINARY IDD SPECIFICATIONS AND TEST CONDITIONS Parameter Symbol Conditions One device bank active; Active-Precharge; tRC = tRC(MIN); tCK = tCK(MIN); DQ, DM and DQS inputs change once per clock cycle; Address and control inputs change once every two clock cycles One device bank; Active-Read-Precharge; BL = 4; tRC = tRC(MIN); tCK = tCK(MIN); IOUT = 0mA; Address and control inputs change once per clock cycle All device banks are idle; Power-down mode; tCK = tCK(MIN); CKE = LOW CS# = HIGH; All device banks are idle; tCK = tCK(MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS and DM One device bank active; Power-down mode; tCK = tCK(MIN); CKE = LOW CS# = HIGH; CKE = HIGH; One device bank active; tRC = tRAS(MAX); tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle; Address and other control inputs changing once per clock cycle Burst = 2; Reads; Continuous burst; One device bank active; Address and other control inputs changing once per clock cycle; tCK = tCK(MIN); IOUT = 0mA Burst = 2; Writes; Continuous burst; One device bank active; Address and other control inputs changing once per clock cycle; tCK = tCK(MIN); DQ, DM and DQS inputs change twice per clock cycle tRC = tRFC(MIN) CKE < 0.2V Four device bank interleaving Reads Burst = 4 with auto precharge; tRC = tRFC(MIN); tCK = tCK(MIN); Address and control inputs change only during Active READ, or WRITE commands DDR333 @ CL = 2.5 945 Unit Operating current IDD0* mA Operating current Percharge powerdown standby current Idle standby current Active power-down standby current Active standby current Operating current IDD1* IDD2P** 1215 45 mA mA IDD2F** 270 mA IDD3P** 270 mA IDD3N** 405 mA IDD4R* 1260 mA Operating current Auto refresh current Self refresh current Orerating current IDD4W* IDD5** IDD6** IDD7* 1350 1845 45 3240 mA mA mA mA Note: These specifications apply to modules built with Samsung components only. * Value calculated as one module rank in this operation condition and other module rank in IDD2P (CKE low) mode. ** Value calculated as all module ranks in this operation condition. Octobert 2005 Rev. 0 5 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data into Read command Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width Address and Control Input setup time (fast) Address and Control Input hold time (fast) Address and Control Input setup time (slow) Address and Control Input hold time (slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Symbol tRC tRFC tRAS tRCD tRP tRRD tWR tWTR tCK tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tISf tIHf tIS tIHS tHZ tLZ 335 Min 60 72 42 18 18 12 15 1 6 0.45 0.55 -0.6 -0.7 -- 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.8 0.8 -0.7 -0.7 Max Unit ns ns ns ns ns ns ns tCK ns tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns 70K CL = 2.5 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 +0.7 +0.7 Note: These specifications apply to modules built with Samsung components only. Octobert 2005 Rev. 0 6 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY DDR SDRAM COMPONENT ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS (continued) Parameter Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time Note: These specifications apply to modules built with Samsung components only. Symbol tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tRAL 335 Min 12 0.45 0.45 2.2 1.75 75 200 tHP-tQHS tCLmin or tCHmin 0.4 18 (tWR/tCK) + (tRP/tCK) Max Unit ns ns ns ns ns ns tCK us ns ns ns ns tCK 7.8 -- -- 0.55 0.6 AC OPERATING TEST CONDITIONS VCC = 2.5V, VCCQ = 2.5V, 0C TA 70C Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) Min VREF +0.31 0.7 0.5*VCCQ-0.2 Parameter/Condition Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Differential Voltage, CK and CK# inputs Input Crossing Point Voltage, CK and CK# inputs Max VREF -0.31 VCCQ+0.6 0.5*VCCQ+0.2 Unit V V V V Note 1 1 NOTES: 1. VIH overshoot: VIH = VCCQ +1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL = -1.5V for a pulse width < 3ns and the pulse can not be greater than 1/3 of the cycle rate. October 2005 Rev. 0 7 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY ORDERING INFORMATION FOR D3 Part Number WV3EG64M72ETSU335D3xG Speed 166MHz/333Mb/s CAS Latency 2.5 tRCD 3 tRP 3 Height* 28.58 (1.125") Temperature 0C to 70C NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option PACKAGE DIMENSIONS FOR D3 FRONT VIEW 133.50 (5.256) 133.20 (5.244) 128.95 (5.077) TYP 4.10(0 .161) (4X) 3.90(0.154) 28.725 (1.131) 28.425 (1.119) 2.50 (0.098) D (2X) 2.30 (0.091) TYP. 17.80 (0.700) TYP. 3.30 (0.130) MAX PIN 1 2.30 (0.091) TYP. 1.27 (0.050) TYP. 1.00 (0.039) TYP. 6.35 (0.250) TYP. PIN 92 120.65 (4.750) TYP. BACK VIEW 1.37 (0.054) 1.17 (0.046) PIN 184 49.53 (1.95) TYP. 1.80 (0.071) TYP 64.77 (2.55) TYP. PIN 93 3.80 (0.150) 10.00 (0.394) TYP. TYP. * ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES) October 2005 Rev. 0 8 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs WV3EG64M72ETSU-D3 PRELIMINARY PART NUMBERING GUIDE WV 3 E G 72M 64 E T S U xxx D3 x G WEDC MEMORY (SDRAM) DDR GOLD DEPTH BUS WIDTH COMPONENT WIDTH (x8) TSOP 2.5V UNBUFFERED SPEED (MHz) PACKAGE 184 PIN COMPONENT VENDOR NAME (M = Micron) (S = Samsung) G = ROHS COMPLIANT Octobert 2005 Rev. 0 9 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com White Electronic Designs Document Title 512MB - 64Mx72 DDR SDRAM UNBUFFERED WV3EG64M72ETSU-D3 PRELIMINARY Revision History Rev # Rev 0 History Created Release Date 10-05 Status Preliminary October 2005 Rev. 0 10 White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com |
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